(1) Field of the Invention
The present invention relates to a functional block design method for designing a functional block including memory and a functional block design apparatus for carrying out the method, and more particularly, to a functional block design method for designing a functional block incorporating therein memory with a desired capacity complying with an order and a functional block design apparatus for carrying out the method.
(2) Description of the Related Art
Nowadays various electronic devices are controlled by LSI (Large Scale Integrated) control units (system LSIs) incorporated therein. In recent years, there has been an increasing demand for curtailment of the period needed for the development of such electronic devices so that the devices can be promptly placed on the market. Thus, also in the case of system LSIs incorporated in electronic devices, there has been a demand for shorter-period development of optimum system LSIs with high functionality.
Techniques for developing a system LSI in a short period of time include a method wherein circuit design and verification of operation are carried out for each function of the system LSI. A circuit block (functional block) associated with each function is called macro, and macros required to control an electronic device are combined to develop a system LSI necessary for the electronic device.
Among the macros constituting a system LSI, a macro including a CPU (Central Processing Unit) core circuit is referred to as CPU macro. A macro including a DSP (Digital Signal Processor) also comes under the concept of CPU macro.
The CPU macro includes a peripheral circuit, a memory circuit, etc. besides the CPU core circuit. By having a memory circuit built into the CPU macro, it is possible to verify, within the CPU core circuit, the operation of a basic process (e.g., a process requiring high-speed execution) executed by the CPU core circuit.
Meanwhile, the memory configuration (e.g., capacities of ROM (Read Only Memory) and RAM (Random Access Memory)) of the CPU macro is determined in accordance with the electronic device as an end product. Accordingly, the floor plan of the CPU macro needs to be determined for each product in which the system LSI is to incorporated. Thus, in order to speed up the development of system LSI, curtailment of the period needed for designing the floor plan of the CPU macro is also demanded.
FIGS. 8A to 8C illustrate conventional floor plans for CPU macros, wherein FIG. 8A shows a first example of floor plan, FIG. 8B shows a second example of floor plan, and FIG. 5C shows a third example of floor plan.
In the case of developing CPU macros, the required memory size/memory configuration varies from product to product, as shown in FIGS. 8A to 8C. Accordingly, the arrangement of the CPU core circuit, peripheral circuit, memory circuit, etc. is determined for individual products. The floor plan is so designed that the CPU macro as a whole may have an aspect ratio (vertical dimension-to-lateral dimension ratio) falling within a predetermined range. This is because the closer to square the aspect ratio is, the more easily an LSI chip can be designed during the development of the whole chip.
For example, in the floor plan shown in FIG. 8A, a CPU macro 910 has a CPU core circuit 911, a peripheral circuit 912 and a plurality of memory circuits 913 arranged therein. The CPU macro 910 is in the form of a rectangle having lateral sides with a length of X1 and vertical sides with a length of Y1, hence the aspect ratio (vertical dimension-to-lateral dimension ratio) being Y1/X1. This CPU macro 910 has a small memory capacity, compared with the other exemplary floor plans.
In the floor plan of FIG. 8B, a CPU macro 920 has a CPU core circuit 921, a peripheral circuit 922 and a plurality of memory circuits 923 arranged therein. The CPU macro 920 has lateral sides with a length of X2 and vertical sides with a length of Y2, and hence the aspect ratio is Y2/X2. The memory capacity of the CPU macro 920 is greater than that of the first example of floor plan but smaller than that of the third example of floor plan.
In the floor plan of FIG. 8C, a CPU macro 930 has a CPU core circuit 931, a peripheral circuit 932 and a plurality of memory circuits 933 arranged therein. The CPU macro 930 has lateral sides with a length of X3 and vertical sides with a length of Y3, and hence the aspect ratio is Y3/X3. This CPU macro 930 has a large memory capacity, compared with the other exemplary floor plans.
Thus, in the case of CPU macros designed in compliance with orders, the memory configuration/memory capacity varies even if the logical structure of the CPU core circuit and peripheral circuit is the same. Conventionally, therefore, floor planning is carried out for each CPU macro by determining the arrangement of the individual circuits so that the aspect ratio may fall within a certain range. Namely, even if the change made to the configuration of a CPU macro designed in the past involves memory capacity only, it is necessary that the CPU core circuit, the peripheral circuit and the memory circuits should individually be rearranged.
Also, in cases where a floor plan is newly prepared, the step of guaranteeing a certain operating frequency needs to be executed.
FIG. 9 illustrates a procedure for designing a CPU macro. First, the customer's specification is determined (Step S91), and then a logic design is prepared in compliance with the customer's specification (Step S92). After the logic design is completed, a floor plan/layout is determined (Step S93). Specifically, a CPU core circuit, a peripheral circuit and a plurality of memory circuits are arranged so that the aspect ratio may be within a predetermined range.
After the floor planning/layout is completed, the process separates into a timing verification procedure (Steps S94 to S98) and a physical verification procedure (Steps S99 to S101).
In the timing verification procedure (Steps S94 to S98), first, an RC extraction process is carried out (Step S94). In this step, a delay is calculated from the resistance (R) and electrostatic capacitance (C) of a plurality of sections in the circuit. Then, based on the extracted RC, timing verification is carried out (Step S95). Namely, it is verified whether signal is transmitted with correct timing as demanded by the logic design. The result of the verification is then checked (Step S96).
If the result of the verification is unsuitable, the CPU macro is again designed from the logic design (Step S92) or from the floor planning/layout (Step S93). Generally, in cases where the result of verification is unsuitable in initial stages, the floor planning/layout (Step S93) is carried out again. If the result of the timing verification becomes unsuitable even though the floor planning/layout (Step S93) is modified a plurality of times, then the logic design (Step S92) is prepared again.
If the result of the verification is suitable, a timing library is created (Step S97). The timing library has registered therein information about the propagation (delay etc.) of signal between the component elements (e.g., flip-flops).
In the physical verification procedure, first, physical verification is carried out (Step S99). As such physical verification, it is verified whether the physical arrangement such as a wiring pitch, for example, satisfies a condition specified by a predetermined rule. The result of the verification is then checked (Step S100).
If the result of the physical verification is unsuitable, the layout decision process of Step S93 is again performed.
If the result of the physical verification is OK, floor plan data and mask pattern data are generated (Step S101). The floor plan data is data indicating, for example, the positions of terminals provided to connect the CPU macro to other circuits. The mask pattern data is data indicating a mask pattern for the CPU macro. Subsequently, the generated timing library, floor plan data and mask pattern data are delivered to the customer.
In this manner, the configuration of the CPU macro whose operation at a certain operating frequency is guaranteed is determined.
Each time a floor plan is prepared anew, however, the timing verification and the physical verification need to be carried out to guarantee the operating frequency, and the floor planning/layout planning must be repeated until these verifications are established. If the floor plan/layout plan is modified, the timing and physical verifications must be again carried out, with the result that much time is needed for the development of CPU macros.